"A wide-range delay-locked loop with a fixed latency of one clock cycle."

Hsiang-Hui Chang et al. (2002)

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DOI: 10.1109/JSSC.2002.800922

access: closed

type: Journal Article

metadata version: 2022-04-04

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Hsiang-Hui Chang, Jyh-Woei Lin, Ching-Yuan Yang, Shen-Iuan Liu:
A wide-range delay-locked loop with a fixed latency of one clock cycle. IEEE J. Solid State Circuits 37(8): 1021-1027 (2002)

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