"A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB ..."

Luca Bertulessi et al. (2019)

> Home

Details and statistics

DOI: 10.1109/JSSC.2019.2940332

access: closed

type: Journal Article

metadata version: 2020-10-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/BertulessiKCGSL19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/BertulessiKCGSL19
Luca Bertulessi, Saleh Karman, Dmytro Cherniak, Alessandro Garghetti, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS. IEEE J. Solid State Circuits 54(12): 3493-3502 (2019)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.