"Architecture level analysis for process variation in synchronous and ..."

Sayed Taha Muhammad et al. (2017)

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DOI: 10.1016/J.JPDC.2016.12.019

access: closed

type: Journal Article

metadata version: 2020-02-22

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Sayed Taha Muhammad, Magdy A. El-Moursy, Ali A. El-Moursy, Hesham F. A. Hamed:
Architecture level analysis for process variation in synchronous and asynchronous Networks-on-Chip. J. Parallel Distributed Comput. 102: 175-185 (2017)

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