"Microarchitecture Level Interconnect Modeling Considering Layout Optimization."

Weiping Liao, Lei He (2005)

> Home

Details and statistics

DOI: 10.1166/JOLPE.2005.036

access: closed

type: Journal Article

metadata version: 2023-03-13

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jolpe/LiaoH05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jolpe/LiaoH05
Weiping Liao, Lei He:
Microarchitecture Level Interconnect Modeling Considering Layout Optimization. J. Low Power Electron. 1(3): 297-308 (2005)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.