"TLP-LDPC: Three-Level Parallel FPGA Architecture for Fast Prototyping of ..."

Yi-Fan Zhang, Lei Sun, Qiang Cao (2022)

> Home

Details and statistics

DOI: 10.1007/S11390-022-1499-9

access: closed

type: Journal Article

metadata version: 2024-10-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jcst/ZhangSC22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jcst/ZhangSC22
Yi-Fan Zhang, Lei Sun, Qiang Cao:
TLP-LDPC: Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis. J. Comput. Sci. Technol. 37(6): 1290-1306 (2022)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.