"Low Power Aging-Aware On-Chip Memory Structure Design by Duty Cycle Balancing."

Shuai Wang et al. (2016)

> Home

Details and statistics

DOI: 10.1142/S0218126616501152

access: closed

type: Journal Article

metadata version: 2020-08-25

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jcsc/WangJZD16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jcsc/WangJZD16
Shuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan:
Low Power Aging-Aware On-Chip Memory Structure Design by Duty Cycle Balancing. J. Circuits Syst. Comput. 25(9): 1650115:1-1650115:24 (2016)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.