"BIST-Based Low Power Test Vector Generator and Minimizing Bulkiness of ..."

J. Praveen, M. N. Shanmukha Swamy (2018)

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DOI: 10.1142/S0218126618500780

access: closed

type: Journal Article

metadata version: 2020-10-26

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J. Praveen, M. N. Shanmukha Swamy:
BIST-Based Low Power Test Vector Generator and Minimizing Bulkiness of VLSI Architecture. J. Circuits Syst. Comput. 27(5): 1850078:1-1850078:18 (2018)

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