"Design and Simulation of a Novel 16T SRAM Cell for Low Power Memory ..."

P. Nagarajan et al. (2024)

> Home

Details and statistics

DOI: 10.1142/S0218126624500038

access: closed

type: Journal Article

metadata version: 2024-03-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jcsc/NagarajanRMD24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jcsc/NagarajanRMD24
P. Nagarajan, M. Renuga, A. Manikandan, S. Dhanasekaran:
Design and Simulation of a Novel 16T SRAM Cell for Low Power Memory Architecture. J. Circuits Syst. Comput. 33(1) (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.