"A High Efficiency 14-28 Gb/s Tunable Receiver Analog Front-End in 65 nm ..."

Shunyu Li et al. (2024)

> Home

Details and statistics

DOI: 10.1142/S0218126624501160

access: closed

type: Journal Article

metadata version: 2024-05-17

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jcsc/LiCZNZY24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jcsc/LiCZNZY24
Shunyu Li, Guangyong Chu, Kezhen Zhu, Pengfei Niu, Shixun Zhang, Guofeng Yang:
A High Efficiency 14-28 Gb/s Tunable Receiver Analog Front-End in 65 nm CMOS Technology. J. Circuits Syst. Comput. 33(7): 2450116:1-2450116:16 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.