"Fully Pipelined FPGA Acceleration of Binary Convolutional Neural Networks ..."

Mengfei Ji et al. (2024)

> Home

Details and statistics

DOI: 10.1142/S0218126624501706

access: closed

type: Journal Article

metadata version: 2024-07-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jcsc/JiACZ24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jcsc/JiACZ24
Mengfei Ji, Zaid Al-Ars, Yuchun Chang, Baolin Zhang:
Fully Pipelined FPGA Acceleration of Binary Convolutional Neural Networks with Neural Architecture Search. J. Circuits Syst. Comput. 33(10) (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.