"A High-Performance Sequential MRU Cache Using Valid-Bit Assistant Search ..."

Hsin-Chuan Chen, Jen-Shiun Chiang (2007)

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DOI: 10.1142/S0218126607003824

access: closed

type: Journal Article

metadata version: 2020-08-25

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Hsin-Chuan Chen, Jen-Shiun Chiang:
A High-Performance Sequential MRU Cache Using Valid-Bit Assistant Search Algorithm. J. Circuits Syst. Comput. 16(4): 613-626 (2007)

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