"Hardware acceleration design of the SHA-3 for high throughput and low area ..."

Argyrios Sideris, Theodora Sanida, Minas Dasygenis (2024)

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DOI: 10.1007/S13389-023-00334-0

access: closed

type: Journal Article

metadata version: 2024-08-04

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Argyrios Sideris, Theodora Sanida, Minas Dasygenis:
Hardware acceleration design of the SHA-3 for high throughput and low area on FPGA. J. Cryptogr. Eng. 14(2): 193-205 (2024)

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