"Low complexity bit-parallel systolic architecture for computing ..."

Yeun-Renn Ting, Erl-Huei Lu, Jau-Yien Lee (2004)

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DOI: 10.1016/J.VLSI.2004.01.003

access: closed

type: Journal Article

metadata version: 2020-02-20

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Yeun-Renn Ting, Erl-Huei Lu, Jau-Yien Lee:
Low complexity bit-parallel systolic architecture for computing C+AB² over a class of GF(2^m). Integr. 37(3): 167-176 (2004)

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