"Optimum transistor sizing of CMOS logic circuits using logical effort ..."

Kunwar Singh et al. (2018)

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DOI: 10.1016/J.VLSI.2017.08.003

access: closed

type: Journal Article

metadata version: 2024-05-07

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Kunwar Singh, Aman Jain, Aviral Mittal, Vinay Yadav, Atul Anshuman Singh, Anmoll Kumar Jain, Maneesha Gupta:
Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms. Integr. 60: 25-38 (2018)

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