"An efficient VLSI architecture design for logarithmic multiplication by ..."

Durgesh Nandan, Jitendra Kanungo, Anurag Mahajan (2017)

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DOI: 10.1016/J.VLSI.2017.02.003

access: closed

type: Journal Article

metadata version: 2020-02-20

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Durgesh Nandan, Jitendra Kanungo, Anurag Mahajan:
An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition. Integr. 58: 134-141 (2017)

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