"Step-by-Step Design of memory hierarchy for heterogeneously-integrated ..."

Chihiro Matsui, Ken Takeuchi (2019)

> Home

Details and statistics

DOI: 10.1016/J.VLSI.2019.09.006

access: closed

type: Journal Article

metadata version: 2020-02-20

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/integration/MatsuiT19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/integration/MatsuiT19
Chihiro Matsui, Ken Takeuchi:
Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage. Integr. 69: 62-74 (2019)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.