


default search action
"Performance analysis of 4:1 MUX APUF Architecture Implemented on Zynq 7000 ..."
Kaveri Hatti, C. Paramasivam (2025)
- Kaveri Hatti, C. Paramasivam:
Performance analysis of 4:1 MUX APUF Architecture Implemented on Zynq 7000 SoC FPGA. Integr. 102: 102379 (2025)

manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.