"A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle ..."

Yun Fang et al. (2018)

> Home

Details and statistics

DOI: 10.1016/J.VLSI.2018.05.011

access: closed

type: Journal Article

metadata version: 2023-07-13

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/integration/FangYSY18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/integration/FangYSY18
Yun Fang, Xiaopeng Yu, Zheng Shi, Kiat Seng Yeo:
A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS. Integr. 63: 87-92 (2018)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.