"0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its ..."

Yohei Nakata et al. (2012)

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DOI: 10.11185/IMT.7.544

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type: Journal Article

metadata version: 2024-08-31

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Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. Inf. Media Technol. 7(2): 544-555 (2012)

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