"Hardware co-simulation for a low complexity PAPR reduction scheme on an FPGA."

Khalid Al-Hussaini et al. (2017)

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DOI: 10.1504/IJWMC.2017.10003984

access: closed

type: Journal Article

metadata version: 2020-07-03

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  - https://dblp.org/rec/journals/ijwmc/Al-HussainiAVHF17
Khalid Al-Hussaini, Borhanuddin Mohd Ali, Pooria Varahram, Shaiful J. Hashim, Ronan Farrell:
Hardware co-simulation for a low complexity PAPR reduction scheme on an FPGA. Int. J. Wirel. Mob. Comput. 12(1): 49-61 (2017)

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