"Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs."

Burhan Khurshid, Roohie Naaz Mir (2016)

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DOI: 10.1504/IJHPSA.2016.076205

access: closed

type: Journal Article

metadata version: 2020-03-24

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Burhan Khurshid, Roohie Naaz Mir:
Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs. Int. J. High Perform. Syst. Archit. 6(1): 28-35 (2016)

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