"Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs."

Chyi-Shiang Hoo, Kanesan Jeevan, Harikrishnan Ramiah (2015)

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DOI: 10.1002/CTA.1939

access: closed

type: Journal Article

metadata version: 2024-10-06

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Chyi-Shiang Hoo, Kanesan Jeevan, Harikrishnan Ramiah:
Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs. Int. J. Circuit Theory Appl. 43(3): 286-306 (2015)

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