"Impact of the RT-level architecture on the power performance of tunnel ..."

Maria J. Avedillo, Juan Núñez (2018)

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DOI: 10.1002/CTA.2398

access: closed

type: Journal Article

metadata version: 2020-05-11

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Maria J. Avedillo, Juan Núñez:
Impact of the RT-level architecture on the power performance of tunnel transistor circuits. Int. J. Circuit Theory Appl. 46(3): 647-655 (2018)

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