"Design-for-test approach of an asynchronous network-on-chip architecture ..."

Xuan-Tu Tran et al. (2009)

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DOI: 10.1049/IET-CDT.2008.0072

access: closed

type: Journal Article

metadata version: 2020-07-14

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Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach:
Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application. IET Comput. Digit. Tech. 3(5): 487-500 (2009)

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