"Low-space bit-serial systolic array architecture for interleaved ..."

Atef Ibrahim (2021)

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DOI: 10.1049/CDT2.12026

access: open

type: Journal Article

metadata version: 2022-04-09

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Atef Ibrahim:
Low-space bit-serial systolic array architecture for interleaved multiplication over GF(2m). IET Comput. Digit. Tech. 15(3): 223-229 (2021)

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