"Low-power and area efficient binary coded decimal adder design using a ..."

Zarrin Tasnim Sworna et al. (2016)

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DOI: 10.1049/IET-CDS.2015.0213

access: closed

type: Journal Article

metadata version: 2020-09-10

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Zarrin Tasnim Sworna, Mubin Ul Haque, Nazma Tara, Hafiz Md. Hasan Babu, Ashis Kumer Biswas:
Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array. IET Circuits Devices Syst. 10(3): 163-172 (2016)

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