"Design of 10T SRAM cell with improved read performance and expanded write ..."

Ashish Sachdeva, V. K. Tomar (2021)

> Home

Details and statistics

DOI: 10.1049/CDS2.12006

access: open

type: Journal Article

metadata version: 2022-10-24

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/iet-cds/SachdevaT21
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/iet-cds/SachdevaT21
Ashish Sachdeva, V. K. Tomar:
Design of 10T SRAM cell with improved read performance and expanded write margin. IET Circuits Devices Syst. 15(1): 42-64 (2021)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.