"Efficient FPGA based architecture for high-order FIR filtering using ..."

Mountassar Maamoun et al. (2021)

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DOI: 10.1049/CDS2.12043

access: open

type: Journal Article

metadata version: 2023-08-06

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  - journals/iet-cds/MaamounHDSZCB21
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  - https://dblp.org/rec/journals/iet-cds/MaamounHDSZCB21
Mountassar Maamoun, Adnane Hassani, Samir Dahmani, Hocine Ait Saadi, Ghania Zerari, Noureddine Chabini, Rachid Beguenane:
Efficient FPGA based architecture for high-order FIR filtering using simultaneous DSP and LUT reduced utilization. IET Circuits Devices Syst. 15(5): 475-484 (2021)

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