"Packet Processing Architecture with Off-Chip Last Level Cache Using ..."

Tomohiro Korikawa et al. (2021)

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DOI: —

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type: Journal Article

metadata version: 2021-05-17

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Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki:
Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM. IEICE Trans. Commun. 104-B(2): 149-157 (2021)

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