"Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in ..."

Sungjae Kim, Hyungwoo Lee, Juho Kim (2002)

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type: Journal Article

metadata version: 2021-06-09

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Sungjae Kim, Hyungwoo Lee, Juho Kim:
Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(1): 234-240 (2002)

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