"Design and Performance of a Sub-Nano-Ampere Two-Stage Power Management ..."

Mamoru Ugajin et al. (2011)

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DOI: 10.1587/TRANSELE.E94.C.1206

access: closed

type: Journal Article

metadata version: 2020-04-11

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Mamoru Ugajin, Toshishige Shimamura, Shin'ichiro Mutoh, Mitsuru Harada:
Design and Performance of a Sub-Nano-Ampere Two-Stage Power Management Circuit in 0.35-µm CMOS for Dust-Size Sensor Nodes. IEICE Trans. Electron. 94-C(7): 1206-1211 (2011)

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