"Reduced Reconfigurable Logic Circuit Design Based on Double Gate CNTFETs ..."

Hiroshi Ninomiya, Manabu Kobayashi, Shigeyoshi Watanabe (2013)

> Home

Details and statistics

DOI: 10.1587/TRANSFUN.E96.A.356

access: closed

type: Journal Article

metadata version: 2020-04-11

- view
  authority control:
- export record
  dblp key:
  - journals/ieicet/NinomiyaKW13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ieicet/NinomiyaKW13
Hiroshi Ninomiya, Manabu Kobayashi, Shigeyoshi Watanabe:
Reduced Reconfigurable Logic Circuit Design Based on Double Gate CNTFETs Using Ambipolar Binary Decision Diagram. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(1): 356-359 (2013)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.