"Study of Reducing Circuit Scale Associated with Bit Depth Expansion Using ..."

Akihiro Nagase et al. (2014)

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DOI: 10.1587/TRANSINF.E97.D.1283

access: closed

type: Journal Article

metadata version: 2020-04-11

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Akihiro Nagase, Nami Nakano, Masako Asamura, Jun Someya, Gosuke Ohashi:
Study of Reducing Circuit Scale Associated with Bit Depth Expansion Using Predictive Gradation Detection Algorithm. IEICE Trans. Inf. Syst. 97-D(5): 1283-1292 (2014)

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