"A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS ..."

Yasuhiro Morita et al. (2006)

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DOI: 10.1093/IETFEC/E89-A.12.3634

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type: Journal Article

metadata version: 2024-03-11

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Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 0.3-V Operating, V_th-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3634-3641 (2006)

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