"A Sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature ..."

Kosuke Mizuno et al. (2013)

> Home

Details and statistics

DOI: 10.1587/TRANSELE.E96.C.433

access: closed

type: Journal Article

metadata version: 2024-03-11

- view
  authority control:
- export record
  dblp key:
  - journals/ieicet/MizunoTTIKY13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ieicet/MizunoTTIKY13
Kosuke Mizuno, Kenta Takagi, Yosuke Terachi, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video. IEICE Trans. Electron. 96-C(4): 433-443 (2013)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.