"Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells."

Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada (2005)

> Home

Details and statistics

DOI: 10.1093/IETFEC/E88-A.12.3485

access: closed

type: Journal Article

metadata version: 2020-04-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/ieicet/IizukaIA05a
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ieicet/IizukaIA05a
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3485-3491 (2005)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.