"A 10-bit 100 MS/s Successive Approximation Register Analog-To-Digital ..."

Jhin-Fang Huang, Wen-Cheng Lai, Cheng-Gu Hsieh (2014)

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DOI: 10.1587/TRANSELE.E97.C.833

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type: Journal Article

metadata version: 2022-12-07

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Jhin-Fang Huang, Wen-Cheng Lai, Cheng-Gu Hsieh:
A 10-bit 100 MS/s Successive Approximation Register Analog-To-Digital Converter Design. IEICE Trans. Electron. 97-C(8): 833-836 (2014)

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