"A Method for Diagnosing Bridging Fault between a Gate Signal Line and a ..."

Yoshinobu Higami et al. (2017)

> Home

Details and statistics

DOI: 10.1587/TRANSINF.2016EDL8210

access: closed

type: Journal Article

metadata version: 2020-06-15

- view
  authority control:
- export record
  dblp key:
  - journals/ieicet/HigamiWTKS17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/ieicet/HigamiWTKS17
Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line. IEICE Trans. Inf. Syst. 100-D(9): 2224-2227 (2017)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.