"A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with ..."

Chengxian Pan et al. (2022)

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DOI: 10.1587/ELEX.19.20220432

access: open

type: Journal Article

metadata version: 2023-02-15

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Chengxian Pan, Chunqi Shi, Guoliang Zhao, Boxiao Liu, Leilei Huang, Runxi Zhang:
A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO. IEICE Electron. Express 19(24): 20220432 (2022)

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