"Logic area reduction using the deep trench isolation technique based on 40 ..."

Yuan Du et al. (2017)

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DOI: 10.1587/ELEX.14.20170628

access: open

type: Journal Article

metadata version: 2021-02-12

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  - journals/ieiceee/DuYJLSC17
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  - https://dblp.org/rec/journals/ieiceee/DuYJLSC17
Yuan Du, Yong Ye, Weiliang Jing, Xiaoyun Li, Zhitang Song, Bomy Chen:
Logic area reduction using the deep trench isolation technique based on 40 nm embedded PCM process. IEICE Electron. Express 14(15): 20170628 (2017)

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