"A 1.5-5.0 Gb/s clock and data recovery circuit with dual-PFD ..."

Dong-Ho Choi, Changsik Yoo (2014)

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DOI: 10.1587/ELEX.11.20140351

access: open

type: Journal Article

metadata version: 2021-02-12

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Dong-Ho Choi, Changsik Yoo:
A 1.5-5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop. IEICE Electron. Express 11(11): 20140351 (2014)

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