default search action
"High-Speed FPGA Implementation of the SIKE Based on An Ultra-Low-Latency ..."
Jing Tian, Bo Wu, Zhongfeng Wang (2020)
- Jing Tian, Bo Wu, Zhongfeng Wang:
High-Speed FPGA Implementation of the SIKE Based on An Ultra-Low-Latency Modular Multiplier. IACR Cryptol. ePrint Arch. 2020: 1125 (2020)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.