"A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers."

Muhammad Nummer, Manoj Sachdev (2003)

> Home

Details and statistics

DOI: 10.1023/A:1023753231177

access: closed

type: Journal Article

metadata version: 2020-09-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/et/NummerS03
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/et/NummerS03
Muhammad Nummer, Manoj Sachdev:
A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers. J. Electron. Test. 19(3): 299-314 (2003)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.