"A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design."

Yingchun Lu et al. (2022)

> Home

Details and statistics

DOI: 10.1007/S10836-022-05989-X

access: closed

type: Journal Article

metadata version: 2024-04-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/et/LuHWWYLYH22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/et/LuHWWYLYH22
Yingchun Lu, Guangzhen Hu, Jianan Wang, Hao Wang, Liang Yao, Huaguo Liang, Maoxiang Yi, Zhengfeng Huang:
A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design. J. Electron. Test. 38(1): 63-76 (2022)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.