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"Gate-Level Design Methodology for Side-Channel Resistant Logic Styles ..."

Ignacio M. Delgado-Lozano et al. (2022)

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DOI: 10.1109/LES.2021.3122395

access: closed

type: Journal Article

metadata version: 2022-06-23

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Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta:
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs. IEEE Embed. Syst. Lett. 14(2): 99-102 (2022)

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