"Reordering Algorithm for Minimizing Test Power in VLSI Circuits."

K. Paramasivam, K. Gunavathi (2007)

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DOI: —

access: open

type: Journal Article

metadata version: 2020-09-29

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  - https://dblp.org/rec/journals/engl/ParamasivamG07
K. Paramasivam, K. Gunavathi:
Reordering Algorithm for Minimizing Test Power in VLSI Circuits. Eng. Lett. 14(1): 78-83 (2007)

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