"Specification, Planning, and Synthesis in a VHDL Design Environment."

Vijay Nagasamy, Neerav Berry, Carlos Dangelo (1992)

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DOI: 10.1109/54.143146

access: closed

type: Journal Article

metadata version: 2020-05-17

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Vijay Nagasamy, Neerav Berry, Carlos Dangelo:
Specification, Planning, and Synthesis in a VHDL Design Environment. IEEE Des. Test Comput. 9(2): 58-68 (1992)

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