"A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors."

Gabriel Torrens et al. (2024)

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DOI: 10.48550/ARXIV.2411.18114

access: open

type: Informal or Other Publication

metadata version: 2025-01-01

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  - journals/corr/abs-2411-18114
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  - https://dblp.org/rec/journals/corr/abs-2411-18114
Gabriel Torrens, Bartomeu Alorda, Cristian Carmona, Daniel Malagón-Periánez, Jaume Segura, Sebastià Antoni Bota:
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors. CoRR abs/2411.18114 (2024)

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