"Generic System Verilog Universal Verification Methodology based Reusable ..."

Abhishek Jain et al. (2013)

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DOI: —

access: open

type: Informal or Other Publication

metadata version: 2018-08-13

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  - electronic edition @ arxiv.org (open access)
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  dblp key:
  - journals/corr/abs-1301-2858
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  persistent URL:
  - https://dblp.org/rec/journals/corr/abs-1301-2858
Abhishek Jain, Giuseppe Bonanno, Hima Gupta, Ajay Goyal:
Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs. CoRR abs/1301.2858 (2013)

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