"A simple 1-byte 1-clock RC4 design and its efficient implementation in ..."

Rourab Paul et al. (2012)

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DOI: —

access: open

type: Informal or Other Publication

metadata version: 2018-08-13

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  - electronic edition @ arxiv.org (open access)
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  dblp key:
  - journals/corr/abs-1205-1737
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  - https://dblp.org/rec/journals/corr/abs-1205-1737
Rourab Paul, Sangeet Saha, J. K. M. Sadique Uz Zaman, Suman Das, Amlan Chakrabarti, Ranjan Ghosh:
A simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication. CoRR abs/1205.1737 (2012)

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